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The Model 4200-PIV-Q package is designed for quiescent point pulsing for scaled-down RF transistors, such as HEMT and FET devices in III-V or LDMOS technologies. This package supports a number of new pulse testing capabilities by combining multiple Model 4205-PG2s and the Model 4200-SCP2HR Oscilloscope. These new capabilities include dual-channel pulsing (i.e., for pulsing on both the gate and the drain simultaneously), higher power pulsing than the Model 4200-PIV-A package, and pulsing from a non-zero quiescent point. Pulse widths can be adjusted from 500ns to near-DC, and the same setup can also be used for performing true DC tests without re-cabling the system. The software controls sourcing from the pulse generators and data acquisition with the digital oscilloscope to automate a variety of pulse I-V tests. The Model 4200-SCSs proven interface handles instrument setup and control, as well as data storage and presentation. The innovative software provides both cable compensation and load-line ccompensation, producing DC-like I-V transistor curves, such as a VDS - ID family of curves and VGS - ID for voltage threshold extraction. The Model PIV-Q package will be useful for a variety of large signal tests on high frequency transistors, as well as for investigation of dispersion phenomena and device performance at speed. It also offers a good approach for avoiding the isothermal problems inherent in DC testing.
The Model PIV-Q package provides an easy-to-understand solution right out of the box, while offering access to the pulse generators and scope for general purpose pulse and scope applications. |
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应用 |
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Dual-channel pulse I-V testing for III-V and LDMOS:
Pulse voltage on Gate and Drain
Measure: gate current, drain voltage and current
±20V pulses for the gate, ±38V pulses for the drain
Pulse Widths: 500ns to 999ms
Included tests:
VDS - ID: Both pulse and DC
VGS - ID: Both pulse and DC
Single-pulse scope view: Useful for setup validation, pulse width optimization, prototyping of novel pulse tests |
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